The ever increasing advances in silicon process technology and reduction of transistor geometry makes static power (leakage) a more significant contributor in the power budget of integrated circuit devices, such as processors (CPUs). To attempt to reduce power consumption, some devices have been equipped to enter one or more reduced power states. In a reduced power state, a reduced clock frequency and/or operating voltage may be employed for the device.
For microprocessors, currently known Advanced Configuration and Power Interface (ACPI) and ACPI-based low-power states have been employed to reduce dynamic power consumption and reduce central processing unit (CPU) static power. ACPI is an open industry standard that defines common interfaces for hardware recognition, motherboard and device configuration, and power management. A widely recognized element of ACPI is power management—giving the operating system (OS) control of power management, in contrast with prior models where power management control was mainly under the control of the Basic Input/Output System (BIOS), with limited intervention from the OS. In ACPI, BIOS provides the OS with methods for directly controlling the low-level details of the hardware, providing the OS with nearly complete control over the power saving schemes.
The ACPI standard specifies various groups of states, among them global states, device states, performance states, and processor states. For example, the ACPI standard defines four processor power states, C0-C3. C0 is the operating state. C1 (often referred to as Halt state) is a state in which the processor is not executing instructions, but can (essentially) instantaneously return to an executing state. C2 (often known as Stop-Clock state) is a state in which the processor stops clocks but maintains cache contents and all software-visible state data. Because cache contents are maintained in C2, the processor must still service coherency probes. C3 (often known as Sleep state) is a state in which the processor maintains cache contents and software state, but lowers voltage to a level sufficient to maintain the saved state. While the ACPI standard specifies 4 states (C0-C3), processors can have independently-defined hardware states beyond C3 representing progressively lower power states. Incremental improvements can be made by flushing cache contents so that the core no longer needs to participate in coherency probes (C5 state). The lowest power state is achieved when the processor cache contents and software context are saved and supply voltage is reduced to eliminate leakage. (C6 state).
On the system level, the APCI standard defines various system sleep states. The G0 (S0) state is the working state. G1 is a sleep state that is subdivided into the S1 state (all processor caches are flushed, and the CPU(s) stop executing instructions; power to the CPU rails and RAM is maintained; devices that do not indicate they must remain on may be powered down), the S2 state (CPU rails powered off), the S3 state (commonly referred to as standby, sleep, or suspend to RAM; RAM remains powered), and the S4 state (commonly referred to as hibernation or suspend to disk; all contents of main memory are saved to non-volatile memory such as a hard drive, and is powered down). The G2 state, or S5 state, is similar to a G3 mechanical off state, but some components remain powered so the computer can “wake” from input from the keyboard, clock, modem, LAN, or USB device. A connected standby system sleep, S03, is similar to a system sleep, S3, but maintains network connectivity. Another difference with the S03 state is that it is controlled by hardware or firmware in the processor and is transparent to the operating system, in that the operating system still sees the system as being in an S0 state.
The S3 or S03 states are the lowest sleep states that maintain some functionality, such as memory state. However, the processor states are lost and the processors are subjected to a reset prior to becoming operable. In addition, all processor cores and the graphics processing unit are reset and brought to an operable state. In many cases, the event triggering the wake-up event does not require full system operability.
This section of this document is intended to introduce various aspects of the art that may be related to different aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the different aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.